Multi-channel precision synchronous voltage-to-frequency converter

ABSTRACT

A multi-channel synchronous voltage-to-frequency converter (SVFC) realized in an integrated semiconductor circuit. The multi-channel SVFC having an operational amplifier adapted to receive an analog data signal to be converted and a reset signal, the operational amplifier integrating the sum of the analog signal and the reset signal and generating an output signal as a function of the integrated sum; a comparator coupled to receive the integrated sum and a reference level signal, the comparator outputting a logic level signal as a function of the received reference level signal; a digital logic circuit in response to an external clock signal, the digital logic circuit receiving the logic level signal and generating a reset control signal and a frequency output pulse as a function of the logic level signal; and a reset source switch receiving the reset control signal and outputting the reset signal.

[0001] This application claims the benefit of U.S. ProvisionalApplication Serial No. 60/249,938, filed in the name of Douglas C.MacGugan on Sep. 1, 2000, the complete disclosure of which isincorporated herein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates generally to voltage-to-frequencyconverters, and in particular to a methods and apparatuses for providingmulti-channel capability in a synchronous voltage-to-frequency converterrealized in an integrated circuit.

BACKGROUND OF THE INVENTION

[0003] Several types of precision sensor systems are known that providean analog signal output. In order to provide useful information to modemdigital systems, the analog signal output of these precision sensorsmust be translated to digital format. Furthermore, many applicationsrequire the translation from analog to digital to be accomplishedwithout loss of data during the conversion sequence. Typicalapplications requiring a “no-loss” conversion include, but are notlimited to, Inertial Guidance and Navigation systems, Inertial PointingSystems, and steering and attitude determination systems. Commonsuccessive approximation (SA) analog-to-digital converters (ADC) operateusing a “hold” time, which is not compatible with such a no-lossconversion.

[0004] Analog to digital conversion without loss of signal duringconversion also accommodates digital filtering techniques, such asaveraging over multiple samples, wherein quantization errors are reducedmuch faster, i. e, by 1/N rather than 1/{square root}{square root over(N)}, where: N is the number of samples used in averaging.

[0005] Voltage-To-Frequency Converters (VFC's) are a form of ADC thatprovide no-loss conversion. Different VFC's use different approaches toconvert the analog signal directly into a frequency proportional to thesignal. This frequency is then counted by electronic counter means,usually in a processing or control system, to complete the digitaloutput.

[0006] A synchronous VFC or SVFC is a form of VFC that is available forprecision systems. Typically, the SVFC utilizes an external clock tosynchronize the frequency output. The SVFC is more precise than the VFCbecause the counting method of the frequency is synchronized to theinput clock of the VFC, which eliminates any errors on the counteddigital output due to clock aging or other clock error effects. Anyclocking error that does occur is a common mode error between the VFCand the counting electronics. This type of error is normally eliminatedin the conversion process. Unfortunately, most available SVFC devicesavailable have limited capability such that they can only handle onechannel of analog conversion. Additionally, the available SVFCintegrated devices typically consume large amount of power relative tothe power consumption desired of a semiconductor circuit.

SUMMARY OF THE INVENTION

[0007] The present invention provides a synchronous voltage-to-frequencyconverter that overcomes the limitations of the prior art by providing amulti-channel capability in a synchronous voltage-to-frequency converterrealized in an integrated semiconductor circuit that minimizes powerconsumption.

[0008] According to one aspect of the invention, the multi-channelsynchronous voltage-to-frequency converter includes an integratoroperational amplifier adapted to receive both an analog data signal tobe converted and a reset signal, the integrator operational amplifierbeing structured to integrate the sum of the analog signal and the resetsignal and to generate an output signal as a function of the integratedsum; a comparator coupled to receive the output signal of the integratorand a reference level signal, the comparator being structured to outputa logic level signal as a function of the received reference levelsignal; a digital logic circuit responsive to an external clock signal,the digital logic circuit coupled to receive the logic level signal andbeing structured to generate a reset control signal and a frequencyoutput pulse as a function of the logic level signal; and a reset sourceswitch coupled to receive the reset control signal and being structuredto output the reset signal as a function of the reset control signal.

[0009] According to another aspect of the invention, the multi-channelsynchronous voltage-to-frequency converter may also include a trimmingcircuit coupled to an input of the integrator that is adapted to receiveboth an analog data signal to be converted and a reference voltage fortrimming the analog data signal.

[0010] According to another aspect of the invention, the multi-channelsynchronous voltage-to-frequency converter may also include a clockphasing circuit adapted to receive the external clock signal and tooutput the clock signal controlling the digital logic circuit, the clockphasing circuit being structured to phase a plurality of frequencyoutput pulses generated by the digital logic circuit as a function ofthe number of channels of the multi-channel SVFC circuit. The clockphasing circuit may be a digital divider and phase shifter circuit.

[0011] According to another aspect of the invention, the multi-channelsynchronous voltage-to-frequency converter may also include a self-testcircuit coupled to an input to a summing junction of the operationalamplifier between the summing junction and analog data signal to beconverted. The self-test circuit may be implemented as a MOSFET switchstructured to present an essentially zero impedance path for the analogdata signal to be converted.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The foregoing aspects and many of the attendant advantages ofthis invention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

[0013]FIG. 1 shows the invention embodied as a multi-channel synchronousvoltage-to-frequency converter having phased output pulses and an inputself-test feature; and

[0014]FIG. 2 shows a circuit that embodies the invention in a 4-phaseimplementation.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

[0015] In the Figures, like numerals indicate like elements.

[0016] The present invention is a multi-channel synchronousvoltage-to-frequency converter having phased output pulses and an inputself-test feature.

[0017] The present invention also provides a method of converting ananalog signal to a digital signal without loss.

[0018]FIG. 1 is a functional block diagram showing the inventionembodied as a multi-channel SVFC (synchronous voltage-to-frequencyconverter) circuit 10, including optional phased output pulses and anoptional input self-test feature. In FIG. 1, an input analog data signal12 to be converted is applied to a summing junction 14 of an integratoroperational-amplifier 16, commonly referred to as an “op-amp.” The inputanalog signal 12 is passed through a trimming circuit 18, implemented asa scaling and bias offset resistor array, and applied to the integratorop-amp 16 as a current I_(INPUT). A reset signal current I_(RESET) froma reset current source 20 is also applied to the summing junction 14. Innormal operation, the integrator will integrate the sum of the analogsignal current I_(INPUT) and the reset current I_(RESET).

[0019] The output of the integrator op-amp 16 is a voltage V_(INT) thatis applied to a fast response comparator 22. The comparator 22 is set totrigger at a level established by a precision voltage referencegenerator 24 outputting a precision voltage reference V_(REF). Theprecision voltage reference V_(REF) establishes the trigger level forthe comparator 22 and the non-inverting input reference of the inputop-amp 16. The precision voltage reference V_(REF) also provides thescaling and bias voltage of the trimming circuit 18. This method ofusing the same precision voltage reference V_(REF) for all threecircuits: the op-amp 16, the trimming circuit 18, and the comparator 22,makes the frequency output of the device immune to drift or changes inthe precision voltage reference device 24.

[0020] The output of the comparator 22 is a logic level signal that isapplied to a digital logic circuit 26 consisting mainly of flip-floplogic and clocked by an external clock 28. The output of the digitallogic circuit 26 determines when the reset current I_(RESET) is switchedON and applied to the summing junction 14 of the integrator op-amp 16.The output of the digital logic circuit 26 also generates the desiredfrequency output pulses of the multi-channel SVFC 10 circuit.

[0021] In normal operation, the input analog signal 12 causes a ramp inthe output voltage V_(INT) of the integrator op-amp 16. When this rampedintegrator output voltage V_(INT) crosses the reference voltage V_(REF)applied to the comparator 22, the comparator 22 changes state. A resetswitch signal S_(RESET) is generated by the digital logic circuit 26synchronous with a clock pulse from the external clock 28. The resetswitch signal S_(RESET) causes a reset switch 30 to apply the resetcurrent I_(RESET) to the integrator op-amp 16, which drives the rampedoutput voltage V_(INT) of the integrator op-amp 16 in the oppositedirection. The comparator 22 flips state again as the ramped integratoroutput voltage V_(INT) crosses the reference voltage V_(REF), and thecycle repeats.

[0022] By inspection, the input analog signal 12 is never absent fromthe integrator op-amp 16 during the entire conversion cycle. Therefore,in contrast to the conventional SA ADC devices, no information is lostfrom the signal.

[0023] An optional timing circuit 32 is provided on the input clockingsignal from the external clock 28. The timing circuit 32 is a digitaldivider and phase shifter that phases the multi-channel frequency outputpulses generated by the digital logic circuit 26 as a function of thenumber of channels, whereby the frequency output is equal to 1/n timesthe clock signal generated by the external system clock 28, where n isthe number of channels in the multi-channel SVFC circuit 10.

[0024] The frequency output pulse on each channel only occursout-of-phase with the frequency output pulses on other channels. Thefrequency output pulses are applied to a frequency output pulse buffer34, which provides ordered frequency output pulses in phase with thephased clock signal 28. This method reduces switching noise within theintegrated circuit embodying the multi-channel SVFC circuit 10 of theinvention, reduces spurious power supply spiking due to current surges,and results in lower thermal operations.

[0025] An optional “self-test” feature is implemented in themulti-channel SVFC circuit 10 of the invention as a switch 36, such as aMOSFET switch, on the input to the integrator summing junction 14. Innormal operation, the MOSFET switch 36 presents an essentially zeroimpedance path for the analog signal 12 being converted. However, inself-test mode, the MOSFET switch 36 is actuated to block the analogsignal and provide a known reference current I_(REF) to the integratorsumming junction 14. The MOSFET switch 36 thereby drives the SVFCfrequency to a known frequency. The MOSFET switch 36 is thus usefulduring system power up and reset, and for fault diagnostics. In anintegrated circuit embodying the multi-channel SVFC circuit 10 of theinvention, the MOSFET self-test feature is implemented through a digitallogic switch input to the integrated circuit.

[0026] The combination of the clock phasing circuit 32 with output pulsebuffer 34 and the single precision voltage reference generator 24 incombination with the single system clock 28 permit the SVFC circuit 10of the invention to support multiple channels. This combination of thesingle precision voltage reference generator 24 with the single systemclock 28 ensures that all the channels are matched in performance, whichcauses the ratio of signals to be highly stable. In other words, theratio of X versus Y on channel n verses channel m is highly stable.

[0027] The common utilization of the system clock 28 and voltagereference generator 24 also significantly reduces errors due tocomponent drift, aging and other changes.

[0028]FIG. 2 shows one channel of the multi-channel SVFC circuit 10 ofthe invention embodied as an integrated circuit having at least 4channels of a charge-reset, mixed-mode circuit. Each circuit includesthe essential components of the multi-channel SVFC circuit 10 diagrammedin FIG. 1. The invention is not limited to the exemplary 4-channelcircuit described in FIG. 2, but is applicable to multi-channel SVFCcircuits in general, which are considered equivalents of the describedcircuit 10.

[0029] According to one embodiment of the invention, the multiplechannels of the multi-channel SVFC circuit 10 are implemented in ASIC(application specific integrated circuit) format, whereby a system levelapproach to precision analog signal conversion without loss of data isobtained. Various novel aspects of the invention permit themulti-channel SVFC circuit 10 to be implemented in ASIC format,including phasing clocks to reduce integrated circuit noise, using thecommon voltage reference generator 24 to reduce errors, utilizing adigital approach to enhance performance through long-term stability, andutilizing known circuit design techniques to produce a circuit designconducive to CMOS implementation.

[0030] The multi-channel SVFC circuit 10 of the invention is thusimplemented as multiple SVFC circuits in a high temperaturesilicon-on-insulator (SOI) CMOS architecture. The SOI CMOS architectureprovides a system level SVFC conversion useful in multiple sensorsystems. The SOI CMOS architecture also provides a low power CMOSsolution in a high temperature (225° C.) compatible semi-conductor.Utilizing a circuit design compatible with CMOS and SOI CMOSimplementation results in the lower power consumption, which is aided byactual implementation in ASIC format.

[0031] The SOI CMOS architecture results in lower system level costs,and increased system level reliability through reduction of overallparts count. The SOI CMOS architecture also results in lower powerrequirements and a lower thermal signature. The advantatges ofimplementing the multiple SVFC circuits of the invention in a hightemperature SOI CMOS architecture relate to an enhanced system levelperformance, versus an implementation using either discrete componentsor multiple single-channel SVFCs.

[0032] While the preferred embodiment of the invention has beenillustrated and described, it will be appreciated that various changescan be made therein without departing from the spirit and scope of theinvention.

The embodiments of the invention in which an exclusive property ofprivilege is claimed are defined as follows:
 1. A multi-channel SVFC(synchronous voltage-to-frequency converter) circuit, each channel ofthe circuit comprising: an integrator adapted to receive an analog datasignal and a reset signal, the integrator being structured to integratethe sum of the analog signal and the reset signal and generate an outputsignal as a function of the integrated sum; a comparator coupled toreceive the output signal of the integrator and a reference levelsignal, the comparator being structured to output a logic level signalas a function of the received reference level signal; a digital logiccircuit responsive to a clock signal, the digital logic circuit coupledto receive the logic level signal and structured to generate a resetcontrol signal and a frequency output pulse as a function of the logiclevel signal and in phase with the clock signal; and a reset sourceswitch coupled to receive the reset control signal and structured tooutput the reset signal as a function of the reset control signal. 2.The circuit of claim 1 wherein the integrator is an operationalamplifier having a summing junction adapted to receive the analog datasignal and the reset signal.
 3. The circuit of claim 1, furthercomprising a trimming circuit coupled to an input of the integrator thatis adapted to receive an analog data signal.
 4. The circuit of claim 3,further comprising a voltage reference circuit generating the referencelevel signal received by each of the comparator, the non-invertingjunction of the integrator, and the trimming circuit.
 5. The circuit ofclaim 4 wherein the comparator is a fast response comparator set totrigger at a level established by the voltage reference circuit.
 6. Thecircuit of claim 1 wherein the clock signal is generated by a clockphasing circuit adapted to receive an external clock signal and outputthe clock signal controlling the digital logic circuit, the clockphasing circuit phasing a plurality of frequency output pulses generatedby the digital logic circuit.
 7. The multi-channel SVFC circuit of claim6 wherein the phasing the plurality of frequency output pulses generatedby the digital logic circuit is a function of the number of channels ofthe multi-channel SVFC circuit.
 8. The multi-channel SVFC circuit ofclaim 7 wherein the clock phasing circuit is a digital divider and phaseshifter circuit.
 9. The multi-channel SVFC circuit of claim 1, furthercomprising a self-test circuit coupled between the integrator and aninput to the circuit adapted to receive an analog data signal.
 10. Amulti-channel SVFC (synchronous voltage-to-frequency converter) circuit,each circuit comprising: an integrator operational amplifier having aninput for receiving an input to the circuit and for receiving a resetsignal, the integrator operational amplifier integrating the sum of ananalog signal input of the circuit and the reset signal, and generatingan output voltage; a reference voltage generator generating a referencevoltage; a fast response comparator having an input coupled to theoutput of the reference voltage generator and to the output of theintegrator operational amplifier, the comparator changing state as afunction of the reference voltage and outputting a state logic levelsignal; a digital logic circuit having a first input coupled to theoutput of the comparator and a second input for receiving a clock signalfrom an external clock, the digital logic circuit generating a resetcontrol signal and a plurality of frequency output pulses as a functionof the state logic level signal under the control of an external clock;and a reset source switch having an input coupled to the output of thedigital logic circuit, the reset source switch outputting the resetsignal as a function of the reset control signal and in phase with theexternal clock.
 11. The multi-channel SVFC circuit of claim 10, furthercomprising a clock phasing circuit having an input for receiving a clocksignal from an external clock, the clock phasing circuit coupled to thesecond input of the digital logic circuit for phasing the plurality offrequency output pulses generated by the digital logic circuit.
 12. Themulti-channel SVFC circuit of claim 11 wherein the phasing the pluralityof frequency output pulses generated by the digital logic circuit is afunction of the number of channels of the multi-channel SVFC circuit.13. The multi-channel SVFC circuit of claim 12 wherein the clock phasingcircuit is a digital divider and phase shifter circuit.
 14. Themulti-channel SVFC circuit of claim 10, further comprising a self-testcircuit coupled between the input to the integrator operationalamplifier and the input to the circuit.
 15. The multi-channel SVFCcircuit of claim 10 wherein: the integrator operational amplifierincludes a summing junction; and the input of the integrator operationalamplifier for receiving an input to the circuit and for receiving areset signal is to an input to the summing junction of the integratoroperational amplifier.
 16. The multi-channel SVFC circuit of claim 10wherein the integrator operational amplifier is structured to receive ananalog data signal input as a current.
 17. The multi-channel SVFCcircuit of claim 10 wherein the output voltage generated by theintegrator operational amplifier is generated as a function of theintegrated sum of an analog signal input of the circuit and the resetsignal.
 18. The multi-channel SVFC circuit of claim 10 wherein theintegrator is adapted to receive the input of the circuit as an inputcurrent and to receive the reset signal input as an input current. 19.The multi-channel SVFC circuit of claim 10 wherein the comparator is setto trigger at a level established by the reference voltage generator.20. A multi-channel SVFC (synchronous voltage-to-frequency converter)circuit, comprising: a plurality of SVFC circuits realized in SOI(silicon-on-insulator) CMOS architecture, each circuit comprising: anoperational amplifier adapted for receiving at a summing junctionthereof an analog data signal to be converted by a channel of thecircuit and a reset signal, the operational amplifier structured tointegrate the sum of an analog signal input of the circuit and the resetsignal, and generate an output voltage as a function of the sum of ananalog signal and the reset signal; a reference voltage generatorgenerating a reference voltage; a fast response comparator coupled toreceive the output of the reference voltage generator and the output ofthe operational amplifier, the comparator structured to change state asa function of the reference voltage and output a state logic levelsignal; a digital logic circuit coupled to receive the output of thecomparator and an external clock signal, the digital logic circuitstructured to generate a reset control signal and a plurality offrequency output pulses as a function of the state logic level signalunder the control of the external clock; and a reset source switchcoupled to receive the output of the digital logic circuit, the resetsource switch structured to output the reset signal in response to thereset control signal.
 21. The circuit of claim 20, further comprising aclock phasing circuit coupled to receive an external clock signal andoutput the clock signal controlling the digital logic circuit, the clockphasing circuit structured to phase a plurality of frequency outputpulses generated by the digital logic circuit as a function of thenumber of channels of the multi-channel SVFC circuit.
 22. Themulti-channel SVFC circuit of claim 20, further comprising a self-testcircuit coupled to an input to the integrator summing junction of theoperational amplifier between the summing junction and analog datasignal to be converted, the self-test circuit being a MOSFET switchstructured to present an essentially zero impedance path for the analogdata signal to be converted.